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 Post subject: MPC5121e Support
PostPosted: Thu Feb 21, 2008 10:44 am 
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Genesi

Joined: Fri Sep 24, 2004 1:39 am
Posts: 1422
We are starting to put together a 5121e support team. The 5121e does not support hardware cache coherency which does create some work when one wants to use the 5200B/e300-core code base. If you have some experience with these issues and you are interested in working on some interesting hardware targeted at consumers please let us know.

Consideration will be primarily given to PegasosPPC/ODW and EFIKA developers that have contributed in the past.

Thanks!

R&B :)

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 Post subject: Re: MPC5121e Support
PostPosted: Fri Feb 22, 2008 1:38 am 
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Joined: Mon Jan 08, 2007 3:40 am
Posts: 195
Location: Pinto, Madrid, Spain
Quote:
The 5121e does not support hardware cache coherency
What is this "cache coherency" function? When lacking, does it affect mostly kernels, drivers, or applications?

Yes, I'm making it pretty clear that I'm a completely useless guy.


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 Post subject:
PostPosted: Fri Feb 22, 2008 2:01 am 
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Genesi

Joined: Mon Jan 30, 2006 2:28 am
Posts: 409
Location: Finland
Hi.

Cache coherency is a mechanism that keeps multiple caches of the same data synchronised. This is necessary when one shares a common resource between multiple cores, each having a different cache for this resource.

The 5121e can be seen as a tripple core architecture, and there is (afaik) a problem in keeping the different caches synchronised, especially at high data rates.


Johan.

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 Post subject:
PostPosted: Fri Feb 22, 2008 5:58 am 
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Site Admin

Joined: Fri Sep 24, 2004 1:39 am
Posts: 1589
Location: Austin, TX
The basic problem is that during a DMA operation, peripherals can write into system memory, and the CPU core is not automatically notified.

If any of you guys remember writing drivers or even browsing the exec.library documentation you might remember some functions called CachePreDMA and CachePostDMA. They essentially marked off certain portions of memory so that they were not in cache, and afterwards, made sure that if the CPU wanted to access data, that it would cache new data from memory and not use stale data in the cache. It's the same principle.

Linux has a different way of doing it; since it has better MMU control it marks off a certain portion of memory as cache-inhibited making it slow to access but guaranteed to be valid (it will never be cached). It will also mark certain regions as being purposed for DMA, in the same way as above (it is simply an API abstraction of a common processor feature).

For the basis of this discussion let us assume that this has ZERO performance impact on the processor or peripherals.

The main problem is the way to run a non-cache-coherent kernel vs. a cache-coherent kernel is completely configured at compile time. This means you can't have a single Efika 5200B/8610/5121E kernel, you need a seperate, specially compiled one for the MPC5121E with the right Kconfig flags set. In this case, though, some advantage can be gained by not having to support every other Power platform at the same time, giving some extra efficiency in the size and modularity.

It should be noted that lack of cache coherency for peripherals is not a problem for userspace which really cannot access the hardware or initiate peripheral access without abstraction anyway (/dev devices etc.) - so all the same software packages you run on your Linux distro will work fine. It's just a new kernel and new kernel modules you need. This poses (for us) some problem for all the distributions which ship kernel and certain (audio for example) modules in seperate packages. For SuSE, Fedora and Ubuntu this might be hairy. For CruxPPC it is simply another .config file.

Are we all beginning to see what the scope of this is? Basically we need kernel pokers and kernel builders and to create the kernel build systems for the required distributions so we can have installers, kernels and kernel module support for this processor :)

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PostPosted: Mon Mar 03, 2008 3:14 am 
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Joined: Thu Feb 16, 2006 8:10 pm
Posts: 98
after waiting for a very long time for a general purpose wireless PPC mini board, with the arrival of
The Menlow (x86 core2)platform, is the game finally over for the mass PPC core +wireless on small consumer units ?

http://www.dailywireless.org/2008/03/02 ... lled-atom/

"...
The Menlow platform is now known as the Intel Centrino Atom platform. It will include an Intel Atom processor, Intel 945GSE graphics chipset and a wireless radio.

Atom processors use Intel’s 45nm, hi-k metal gate technology that allows very low power — from 0.6-2.5 watts — with up to 1.8GHz speeds. By comparison, today’s mainstream mobile Core 2 Duo processors are in the 35-watt range.

..."


Image


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PostPosted: Mon Mar 03, 2008 4:34 am 
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Site Admin

Joined: Fri Sep 24, 2004 1:39 am
Posts: 1589
Location: Austin, TX
Quote:
after waiting for a very long time for a general purpose wireless PPC mini board, with the arrival of
The Menlow (x86 core2)platform, is the game finally over for the mass PPC core +wireless on small consumer units?
No. Menlow, like all the rest of the Centrino platforms, is just a recommended bundling of chipsets; Intel state that Centrino branding can only be attained by using their 3-for-3 combination. The wireless is simply PCI Express Mini Card like the 4965AGN board found in most laptops..

All in all Menlow didn't change a thing but the size of the CPU.

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