Matt, please post the new information.

Thanks.

R&B :)

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http://bbrv.blogspot.com

Word from AMD is that A-Link <=> PCI Express compatibility "does not look good" - there are some quirks which make it decidedly not compliant. We're still looking into it though.

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Matt Sealey

Don't take no for an answer! :-)

We might take other answers that mean no :)

There are plenty of ways to design a system board without a southbridge, it would just be a real shame to lose the integration in "favor" of a bunch of discrete chipsets.

That said, using discrete chipsets means we can hand-pick the features, take them off the board for different versions, or add new ones. It also means we can do our own integration - a custom system management controller (like the one on the Efika) might work better for the MPC8610 than the PC-like one in the southbridge, and we won't need to deal with i8259 interrupt cascades..

Both ways have their advantages and disadvantages, neither better or worse as a whole than the other.

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Matt Sealey

What's that "custom system management controller" that the Efika has? You don't mean an internal feature of the MPC5200, do you.
I guess that's something that can't be handled within software, right?

I asked around as well, here's what AMD told me about SB600 connected to any standard PCI-Express port and/or via a PCI-Express switch:
Oh well, a guy can dream can't he? That's part of why I liked the M1575, they at least said they supported such uses, even if it may have been weird as some have suggested. You had me excited Neko before AMD started suggesting otherwise. :p

Bill, all the information you will be able to get is here:

AMD Embedded Developer Support Site

As you learned, the SB600 with other northbridges besides the 690 family is not an AMD validated or supported configuration. You would be pretty much on your own to make it work. There are several things in the NB/SB interface which are non-standard PCIE. For example:

-- Interrupt messages from the NB are sent downstream to the SB. In standard PCIE, interrupt messages are sent upstream from devices to a root complex.

-- They use a reserved opcode for some non-standard link operation.

-- They have some vendor-defined messages between NB/SB.

AMD needs a large business case to enable. The SB600 does not generate a large amount of revenue for AMD. If you want a direct contact to the AMD ECSD Product Manager, send us an email and we will introduce you.

R&B :)

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http://bbrv.blogspot.com

Like I said, AMD suggested otherwise to us too.

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Matt Sealey

No. The MPC5200B has a broken RTC module - while it counts time perfectly well, it has no outside line to a battery (coin cell or whatever) which means on power off, the RTC time resets. You can either supplement it with an external chip or you can reset the time on boot using NTP or so.

So, we have a little chip on the board that handles RTC function. It also has some flash memory (nvram) and handles functions such as the firmware "ac-back-behaviour" setting which allows the system to come back online when the power is cut. It also allows firing an alarm based on any RTC time, which means you can turn them all off by remote and have them come back on at 8:50am in the morning for all the employees if used as a thin client, saving energy etc. And it implements the 4-second power button switch off just like ATX specs suggest.
It is - Linux does it for a lot of platforms - but it's complicated and entirely board-specific. This means every combination of forwarding, cascading, interrupt controllers which exist but are simply not active or used, has to be implemented specifically to act in a certain way in the OS.

Linux then presents a sanitized virtual interrupt number to the rest of the drivers, and deals with the internals of each chip through irq_chip etc. structures and drivers, one for each, one configuration for each board.

Alternatively given that the way Linux does it does not exist on a) Linux 2.4 and early Linux 2.6 versions and b) any other OS, Aura is there such that the complex configuration of the interrupt controller is hidden, and Linux gets an already-sanitized interrupt number and a view of ONE preconfigured, generic interrupt controller. The driver is about ~100 lines but on Linux 2.4, it is about ~25.

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Matt Sealey